As applications for use of liquid crystal display devices increase, an increase in functionality is in progress. In particular, display modes such as MVA (multi-domain vertical alignment) or IPS (in-plane switching) having wide viewing angle characteristics are being developed, and further improvement is in progress.
When performing display of still or moving images, liquid crystal display devices operate such that a voltage applied to a liquid crystal layer is maintained for a prescribed period of time (one frame period, for example) after signal voltages are applied to pixel electrodes. In order to perform such maintenance of voltage more appropriately, in typical liquid crystal display devices, auxiliary capacitance (storage capacitance) is provided in parallel with liquid crystal capacitance. Auxiliary capacitance is formed between an auxiliary capacitance electrode provided in the same layer as gate bus lines, and an auxiliary capacitance opposite electrode is disposed opposite to the auxiliary capacitance electrode across a gate insulating layer, for example.
Also, a technique is known in which auxiliary capacitance is formed by using pixel electrodes and transparent electrodes (hereinafter referred to as lower layer transparent electrode) disposed below the pixel electrodes across an insulating film, and is disclosed in Patent Document 1, for example. According to this technique, auxiliary capacitance is formed by a pair of transparent electrodes, and there is no need to provide separate auxiliary capacitance electrodes made of a metal layer. Thus, it is possible to reduce light-shielding regions, and improve the pixel aperture ratio.
However, when using such a configuration, in order to connect TFTs to pixel electrodes, it is necessary to provide contact holes in the insulating film (hereinafter referred to as upper layer insulating film) interposed between the lower layer transparent electrode and the pixel electrode. As a result, the number of steps for forming contact holes is greater than in conventional configurations.
However, in recent years, the steps for forming contact holes are often performed by dry etching, which can realize a high degree of precision. Typically, dry etching is performed by plasma etching, by which the cross-sectional shape and the like can be controlled with greater ease than with wet etching. However, compared to wet etching, the etching selection ratio (etching rate of film to be removed/etching rate of bottom film (film present below the film to be removed)) is difficult to increase by dry etching, and thus, damage to the bottom film is a concern.
Patent Document 2 discloses a configuration in which a ZnO film is provided on a surface of the drain wiring lines, which are the underlayer, when contact holes are provided over the drain wiring lines and the like in a bottom gate (reverse staggered) TFT. The ZnO film is difficult to etch even with dry etching using an etching gas such as CF4, and therefore, it is possible to appropriately protect the metal film constituting the drain wiring lines. If the drain wiring lines have a structure in which a molybdenum film (or a titanium film or the like) is layered onto an aluminum film, for example, then by providing ZnO film, it is possible to prevent the exposure of the aluminum film as a result of the molybdenum film being removed by etching. If the aluminum film is exposed, then there is a high probability of electrical contact between the aluminum film is exposed, then there is a high probability of electrical contact between the aluminum film and the ITO film to be the pixel electrodes, and thus, this is not preferable.